Industrial Consultancy & Sponsored Research (IC&SR) , IIT Madras

Phase Error Measurement Circuit with Referenceless Gain and Offset Calibration

Categories for this Invention

Category – Electrical Engineering, Circuit Diagnostics

Applications –Electronic System & Design  Manufacturing,  ICT, Automotive

Industry – IT Hardware, Test Equipment, Wireless

Market – Electronic Design Automation Market was valued at USD 12.9 billion in 2022 and is estimated to register a CAGR of over 10% between 2023 and 2032.

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Problem Statement

  • Static phase errors in high-frequency periodic signals cause performance degradation in signal processing ICs, impacting image rejection, error vector magnitude, adjacent channel power ratio, and bit error rate.
  • Current solutions lack accurate phase error measurement without a reference signal and effective compensation methods to eliminate phase errors.

Technology

Gain and Offset-Calibrated 3-State Phase Detector:

  • Utilizes calibrated gain and offset parameters to accurately measure phase differences between signals, crucial for high-frequency signal processing ICs.

Error-Compensating Circuit Architecture:

  • Utilizes a weighted sum of input voltages and one-port networks to achieve tunable delays.

Integrated Circuit Chip for Phase Error Measurement:

  • Develops specialized chips capable of directly measuring phase errors without requiring a reference signal, enabling precise phase correction in various applications.

System-on-Chip Implementation:

  • Integrates phase error measurement functionality into system-on-chip architectures, streamlining the design process and enhancing the efficiency of signal processing systems.

Application in SSB Up/Down Converters and Phase Modulators:

  • Addresses specific needs in communication devices by detecting and correcting phase errors in local oscillator signals and output signals, thereby improving overall system performance.

Key Features / Value Proposition

  • Gain and offset calibration, error-compensating circuit architecture, phase error measurement without a reference, integrated circuit chip implementation.
  • Improved performance in signal processing ICs, communication devices with reduced phase errors, enhanced accuracy, and simplified integration.

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Nagendra Krishnapura

Department of Electrical Engineering

Intellectual Property

  • IITM IDF Ref. 1467
  • IN 487682 (Patent Granted)

Technology Readiness Level

TRL- 4

Technology validated in Lab scale.

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