• The present invention discloses a  system and a method for minimizing delay at a signalized intersection by estimating optimal cycle time for traffic signals under heterogeneous and lane-less traffic conditions.
• A processor-Central processing unit for executing the system’s operations; to compute an intersection delay model and develop the signal control model

Intersection delay model:

• Estimate the delay experienced by one or more vehicles as they pass through the signalized intersection.

Signal control model

• Optimize the signal control model to determine a signal duration that minimizes the delay

1. Intersection Delay Model is  based on the Delay Parameters  such as Saturation Flow Rate in PCU and Number of Parallel Queues
2. Signal Control Model to determine a signal duration for the signalized intersection to minimise the delay experienced by the one or more vehicles.
3. The processor is to communicate the signal duration to at least one traffic signal unit, located proximate to the signalized intersection to control the duration of indication of the traffic signal, the traffic signal comprising at least one of a red signal and a green signal.
4. The processor calculates a Passenger Car Equivalent (PCE) value for the vehicles belonging to various vehicle classes.
5. The processor also calculates the number of parallel channels occurring within a single lane