Industrial Consultancy & Sponsored Research (IC&SR) , IIT Madras
Continuous-time Delta Sigma Modulators With A Plurality Of Switched Capacitor Return-to-zero Digital To Analog Converters
Technology Category/Market
Technology: Continuous-time Delta Sigma Modulators With A Plurality Of Switched Capacitor Return-to-zero Digital To Analog Converters
Category: Electronics & Circuits
Industry: Electronic System & Design Manufacturing (ESDM),
Application: Analog-to-digital conversion (ADC).
Market: The Global Market Size of Delta-sigma Modulator was valued at USD 1.69 Billion in 2023 and is expected to reach USD 3.27 Billion by the end of 2030 with a CAGR of 7.7%
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Problem Statement
- Delta-sigma data modulators are used in analog-to-digital conversion (ADC) applications due to their bandwidth and accuracy.
- Continuous delta-sigma modulators (CTDSMs) are becoming attractive due to their power and area efficiency.
- However, CTDSMs suffer from linearity and jitter performance due to full-scale steps in the feedback waveform.
- Techniques like the switched-capacitor feedback DAC and the Return-to-Zero (SCRZ) DAC address this issue while achieving low jitter sensitivity.
- These techniques provide poor alias rejection despite achieving low jitter sensitivity.
Technology
- The present invention provides a continuous time delta-sigma modulator (CTDSM) with an input node for receiving input voltage, an integrator, a first sub-digital to analog converter (DAC), and a second sub-DAC.
- The integrator includes an OTA and a feedback capacitor.
- The first sub-DAC has a primary, secondary, tertiary, and quaternary auxiliary modules.
- The second sub-DAC samples attenuated input voltage at a sampling rate with a delay
- The method involves receiving an input voltage, sampling attenuated input voltage, and adjusting the sampling rate.
- The invention is not limited to the described embodiments and can be modified without departing from the spirit.
CTDSM 200 Overview
- Input node 202, integrator 204, feedback node 206, first sub-DAC 208a, second sub-DAC 208b.
- Integrator 204 includes operational transconductance amplifier (OTA) 2041 and feedback capacitor 2042.
- OTA 2041 has finite transconductance gm, feedback capacitor has capacitance ‘C’.
- First sub-DAC 208a includes primary auxiliary and secondary modules.
- Second sub-DAC 208a includes tertiary and quaternary modules
Key Features/Value Proposition
Current and Alis Rejection in Circuit
- Current i1 and i2 are RZ pulses, half clock cycle wide.
- Total current i1+i2 is a NRZ pulse.
- Circuit 300 computes alias rejection at fs.
- CTDSM 200 is excited with an input voltage.
Dual-SCRZ DAC for CTDSM
- Proposed CTDSM with dual SCRZ DAC achieves infinite alias rejection, even with OTA having finite transconductance.
- The dual SCRZ DAC samples the voltage of the virtual ground at two instances per cycle.
- Combines low peak-to-average ratio of a non return-to-zero pulse with low jitter sensitivity of a switched capacitor feedback DAC.
- Excellent alias rejection is obtained around fs, even with limited bandwidth of the OTA.
- Measured results show improvements in linearity and alias rejection compared to a modulator using SCRZ DAC.
- Dual SCRZ DAC is robust with respect to clock jitters.
- Voltage of a virtual ground is sampled at two instances per cycle through the dual SCRZ DAC (208a, 208b) while consuming Lower power.
Questions about this Technology?
Contact for Licensing
Research Lab
Prof. Shanthi Pavan
Department of Electrical Engineering.
Intellectual Property
IITM IDF Ref. – 1295
Patent No: IN – 482975
Technology Readiness Level
TRL-4
Experimentally validated in Lab