This present patent disclosure involves a sampler in a full-duplex transceiver system and a method for sampling received signals. this invention introduces a sampler and a method for sampling received signals in a full-duplex system, addressing self-interference and improving signal quality for more efficient wireless communication.

Invention Description:

The Sampler:

This is a component in a full-duplex transceiver system, includes the following key elements:  

• Buffer: Captures amplitude information from both transmitter signal (Tx) and voltage at antenna port.
• Phase Detector: Measures the time delay between the buffered transmitter signal and the voltage at the antenna port.
• Calibration Loop: Controls the delay offset between the transmitter signal & antenna voltage.
• Current Integrator: Generates sampled output.
• Charge Pump: Manages current adjustments.
• Analog to Digital Converter (ADC): Digitizes the sampled output to create the final received signal.

Sampling Process:

• The phase detector performs time-delay sampling at radio frequency using a conversion method.
• The conversion method might involve a voltage-to-delay conversion.

Calibration and Reset:

• The calibration loop includes a calibration loop integrator, and the current integrator is reset before each sampling instance.
• A switch and self-biased inverters are used for calibration to match path delays between the antenna port and the Tx signal paths.