Industrial Consultancy & Sponsored Research (IC&SR) , IIT Madras
Pseudo-interdigitated-corbino Thin Film Transistor with Multi-finger Source and Drain Electrical Contacts
Categories for this Invention
Category- Electronics & Circuits
Industry Classification:
- NIC (2008)-2610- Manufacture of electronic components
- NAICS (2022)- 334413- Semiconductor and Related Device Manufacturing; 333242- Semiconductor Machinery Manufacturing
Applications: Manufacture of Semiconductors, Thin Film Transistors (TFTs), micro-fluidic devices, electrodes, LED displays, RF-ID tags, flexible electronics and communication devices such as antennas, frequency selective surfaces etc.
Market drivers:
Global Thin Film Transistor market was valued at USD 180.9 Million in 2023 and is expected to grow to USD 821.5 Million by the end of 2030 with a CAGR of 24.2%
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Problem Statement
- Thin film transistors (TFTs) are being widely used for various electronic applications. Achieving the three desirable properties of- high transconductance, infinite output resistance, and reduced parasitic leakage in a limited layout space helps in adapting TFTs for logic-TFT or driver-TFT applications.
- TFTs with interdigitated electrodes and Corbino geometry may enable increase in transconductance and reduction in parasitic leakage current with infinite output resistance respectively.
- However, conventional technologies despite using low-cost polymeric semiconductors and Corbino geometry are able to achieve only infinite output resistance while not addressing the desired properties of high transconductance and reduction in parasitic leakage.
- There is a need for a simple fabrication approach to simultaneously achieve excellent electrical isolation, increased transconductance and infinite output resistance while accommodating a large channel width.
Technology
- The novel Psuedo-interdigitated-corbino TFT architecture comprises an arrangement of the source and drain electrodes to accommodate the large channel width (W) of the TFT in an enclosed interdigitated pattern. It is achieved by realizing an equivalent pseudo-corbino structure design as a combination of half-corbino structure and overlapping linear channels.
- TFT using the novel Pseudo-interdigitated-corbino architecture results in infinite output resistance, providing constant drain output current in the saturation region independent of drain bias
- The width of the overlapping linear channel region, denoted as WOV should be equal to or greater than two times the WS For a pseudo-interdigitated-corbino architecture with “n” number of interdigitated overlapping linear channels, the total channel width Wt is given by {n.WOV + (n−2).WS}, where “n” is the number of interdigitated overlapping linear channels.
- The average width of half of the corbino disk (WS) is calculated using the middle circumference approximation {π(R1+R2)/2} as a function of geometrical parameters R1 and R2 i.e., the inner and the outer radius of half of the corbino disk with average channel width WS
- The semiconductor layer is formed over or below the said source and drain electrodes in the top-gate top-contact, top-gate bottom-contact, bottom-gate bottom-contact, or bottom-gatetop-contact configuration.
Key Features / Value Proposition
- The architecture comprises a more readily manufacturable TFT architecture that offers infinite output resistance to provide constant drain current in the saturation region.
- The device showed excellent performance in terms of the device parameters. Whereas, none of the conventional methods overcome the limitations of multi-finger and Corbino TFT architectures in attaining excellent electrical isolation, increased transconductance and infinite output resistance, simultaneously, while accommodating high W/L ratio
- The novel Pseudo-interdigitated-corbino architecture results in an easily manufacturable TFT architecture with reduced fabrication process steps compared to conventional Corbino TFT architecture.
Questions about this Technology?
Contact For Licensing
sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in
Research Lab
Prof. Soumya Dutta
Department of Electrical Engineering
Intellectual Property
- IITM IDF Ref.2789
- Patent Application No: IN 202441025688
Technology Readiness Level
TRL- 4
Experimentally validated in Lab