Industrial Consultancy & Sponsored Research (IC&SR) , IIT Madras
System and Method for Automatic Parallel Code Generation for Graph Algorithms for Multiple Target Architectures
Technology Category/Market
Technology: Graph Domain Specific Language (DSL) Compiler.
Industry: DSL Compiler.
Applications: Hardware & Software for Graph DSL Compiler, System software.
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Targeted Industries
Watermarking IP design,
Electronic circuits
Problem Statement
- Generally, parallelization of graph algorithms is unavoidable with the growth of unstructured & semi-structured data, & graph algorithms have difficult to parallelize due to the inherent irregularity of computation, memory access and communication.
- Further, existing prior framework for exploiting the parallelism on different hardware is difficult for in different application domain.
- However, the existing framework unable to address the issues. Therefore, there is need for a system & method for Graph Domain Specific Solution (DSL) issues.
Technology
- The present invention describes a system & method for automatic parallel code generation for graph algorithms for multiple target architectures.
- A graph domain specific language (DSL) named StarPlat framework enables a user to provide an algorithm specification of graph problems (high level graph specific constructs) & generates parallel code for multiple backends from same algorithm specification.
- Said System comprises a user device, a graph algorithm unit, an intermediate representation unit, a code generator unit, a performance analysis unit and a compiler, shown in figure 1.
Key Features/Value Proposition
Technical Perspective:
- Current method generates the codes for multiple backends simultaneously with efficient parallel processing approach for graph algorithms for multiple target architecture (OpenMP, MPI & CUDA).
Industrial Perspective:
- Both static and dynamic graph algorithm can be taken as input & generates code (library or framework based).
- Applicable to High performance computing & parallel computing, compilers.
Questions about this Technology?
Contact for Licensing
Research Lab
Prof. Rupesh Nasre
Department of Computer Science & Engineering
Intellectual Property
IITM IDF Ref. 2422;
Patent No: 432922
Technology Readiness Level
TRL- 3
Proof of Concept ready & validated.