IDF No 2524 PCB-incorporated based low cost differential mode filter for EMI/ EMC of power electronic converter

PCB-incorporated based low cost differential mode filter for EMI/ EMC of power electronic converter

Technology Category/Market

Technology: A hybrid analog to digital converter and method

Category: Electronics & Circuits

Industry: Electronic System & Design Manufacturing (ESDM), Robotics

Application: Analog to Digital converter

Market: The global market size is expected to grow at a CAGR of 6.3% during 2022-2030, to surpass US$ 6.29 Billion by 2030.

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Problem Statement

  • Electromagnetic interference (EMI) poses significant challenges for power electronic converters, necessitating emissions below international standards.
  • The frequency range for conducted emission noise in power electronics is 150 kHz to 30 MHz, divided into high-frequency and low-frequency zones.
  • Low-frequency zone primarily influences conducted emissions due to converter switching frequency.
  • High-frequency zone includes emissions related to switching transients, especially in Wide Band Gap devices like SiC MOSFETs.
  • Current passive filter designs typically maintain a corner frequency below 150 kHz.
  • PCB-level inductors are utilized in series with X-capacitors, optimizing impedance at around 160 kHz.
  • Biela et al. (2009) present a passive hybrid integrated EMI filter, combining integrated and discrete components.
  • Despite advancements, reliance on bulky common mode chokes and differential mode inductors remains a limitation, especially in achieving inductors with high self-resonant frequency values.

Technology

A filter reduces Differential Mode (DM) emission noise in power converters with an inductance-capacitor circuit and damping resistance, ensuring attenuated noise (Vnf) meets the equation.

Key Features/Value Proposition

Reducing Differential Mode Emission Noise in Power Converters:

  • Utilizes printed circuit board filter.
  • Implements inductance-capacitor circuit with damping resistance.
  • Adjusts length, width, thickness, and distance between PCB traces.
  • Multi-layer PCB for higher inductance and current rating.
  • Device free from magnetic core.
  • Estimates differential mode noise voltage for voltage source inverter.

Questions about this Technology?

Contact for Licensing

Research Lab

Prof. Kamalesh Hatua

Department of Electrical Engineering

Intellectual Property

  • IITM IDF Ref. 2524

  • Patent No: IN 549282

Technology Readiness Level

TRL-6

Technology validated in relevant environment (Industrially relevant enabling technologies)

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IDF No 2313 A hybrid analog to digital converter and method thereof

A hybrid analog to digital converter and method thereof

Technology Category/Market

Technology: A hybrid analog to digital converter and method

Category: Electronics & Circuits

Industry: Electronic System & Design Manufacturing (ESDM), Robotics

Application: Analog to Digital converter

Market: The global market size is expected to grow at a CAGR of 6.3% during 2022-2030, to surpass US$ 6.29 Billion by 2030.

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Problem Statement

  • ADCs enable digitally controlled circuits to communicate with the real world.
  • Analog signals have continuously varying values from various sources and sensors.
  • Digital circuits work with binary numbers with two discrete states.
  • An ADC takes a snapshot of an analog quantity at one instant and produces a digital output code.
  • The number of binary digits used to represent this analog voltage value depends on the resolution of an A/D converter.
  • SSADC, a type of ADC, employs subtraction technique to result in different bit status in different stages of conversion.
  • SSADC has disadvantages such as reduced bandwidth and noise level, making it only implemented for 8-bit or 10-bit resolution.
  • There is a need for an analog to digital converter that can be implemented for bits higher than 8-bit or 10-bit resolution.

Technology

  • Analog to Digital Converter
  • First stage: Comprises first type cascaded blocks,each with a comparator and subtractor.
  • Comparator: Receives input signal and generates digital value when it’s greater than or equal to a corresponding voltage divider value
  • Subtractor: Determines a subtracted voltage value from the input signal and provides it as input to a subsequent cascaded block of the first stage.
  • Second stage: Comprises second type cascaded blocks,each containing first type cascaded blocks .
  • Each first type cascaded block is interlinked to an amplifier , amplifying converted bits.
  • Second stage conversion results in high resolution bits due to amplified converted bits.
  • Amplifier: Amplifies the predefined number of converted bits of each first stage to provide an output to a subsequent second-type cascaded block, enabling higher bit resolution.

Key Features/Value Proposition

Hybrid ADC Structure and Implementation

  • The hybrid ADC includes a Hybrid Successive Subtraction Analog to Digital Converter (HSSADC) with stages and reference types.

Stages and Resolution:

  • The first and second stage blocks may feature an N-reference 5 SSADC, with resolutions of 12-bit, 16-bit, or 20-bit.

Cascading Blocks:

  • The architecture allows for cascading a predefined number of first-type and second-type blocks.

Voltage Divider Implementation:

  • The corresponding voltage divider values for each cascaded block are based on voltage levels within a voltage divider network.

Digital Output Mechanism:

  • The digital value from the comparator indicates a change in the state of the corresponding bit in the first-type cascaded block when the input signal meets or exceeds the voltage divider value.

Bit State Change:

  • The method specifies changing the bit state to at least one of 1 or 0 within the predefined number of bits.

Incorporating N-reference SSADC:

  • An N-reference Successive Subtraction Analog to Digital Converter (SSADC) is used in at least one of the first or second stage blocks.
Questions about this Technology?

Contact for Licensing

Research Lab

Prof. Jagadeesh Kumar V

Department of Electrical Engineering

Intellectual Property

  • IITM IDF Ref. 2313

  • Patent No: IN 551010

Technology Readiness Level

TRL-4

Experimentally validated in Lab

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IDF No 1639 Portable Three-dimensional Waterfall Graphic Print

Portable Three-dimensional Waterfall Graphic Print

Technology Category/Market

Category- Electronics & Circuits /  Green Technology

Industry Classification:

Display Technology ; Entertainment & Event Production ; Advertising & Digital Signage; Automation & Control Systems

Applications:

Signs, lighting, data communication and other signaling, display media, advertisement, patterns & images; advertisements in shopping malls, museums and entertainment shows ; Fountains

Market report:

The global 3D Display market is projected to grow from USD 78.05 Billion in 2024 to USD 260.7 Billion by 2032, with a CAGR of 16.27%

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Problem Statement

  • LED displays are prone to color shifts, environmental pollution, frequent replacements, and high costs due to temperature effects and damage from high electrical currents.
  • Moreover, Current three-dimensional waterfall graphic systems use solenoid valves and microcontrollers but are not portable and often limited in controlling a large number of valves.
  • There is a need for a portable, bi-color waterfall graphic print device that uses water as a display medium, controlled through advanced microcontrollers and solid-state devices.

Technology

  • The system features a cylindrical screen using falling water controlled by solenoid valves, driven by a pre-programmed Arduino microcontroller and custom PCBs for image display.
  • Images are converted to binary data and stored on an SD card. A custom algorithm and OpenCV are used to convert images, enabling continuous pattern generation.
  • A series of solenoid valves control water flow in the display. The solenoids are activated by the Arduino via shift registers, opto-couplers, and TRIAC for precise ON/OFF control
  • The system uses a simple Arduino UNO, TRIAC, and shift registers to control 136 solenoid valves. (16 per board) This setup reduces complexity and improves reliability compared to traditional LED displays.

Key Features/Value Proposition

  • Uses falling water controlled by solenoid valves for displaying 3D graphics, offering a unique and dynamic visual compared to conventional static LED displays.
  • Unlike LED displays, the water-based system requires less maintenance, utilizes water (a renewable resource), and uses far fewer electronic components, making it more eco-friendly.
  • The system operates with fewer electrical components compared to LEDs, consuming less power and being more energy-efficient, making it more sustainable in the long run.
  • Unlike LED systems with numerous electronic components, this device uses a minimal number of components (Arduino, shift registers, TRIAC), reducing complexity and maintenance needs.
  • The modular and compact design, with water circulation and a cylindrical screen, makes the technology easily portable and scalable for use in various applications like museums and exhibitions.
Questions about this Technology?

Contact for Licensing

Research Lab

Deepanath C

Department of Mechanical Engineering

Adhitya M

Department of Metallurgical and Materials Engineering

K Pravllika

Department of Civil Engineering

Chelamkuri Omsrinath

Department of Civil Engineering

Gautam GVS

Department of Mechanical Engineering

Siddartha Tadepalli

Department of Mechanical Engineering

Rohith T

Department of Mechanical Engineering

Vineet Thumuluri

Department of Electrical Engineering

Yogesh Gawade

Department of Metallurgical and Materials Engineering

Prasanth Inavolu

Department of Mechanical Engineering

Intellectual Property

  • IITM IDF Ref 1639
  • IN 544009 Patent Granted

Technology Readiness Level

TRL 9

Actual System Proven in operational environment

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IDF No 1295 Continuous-time Delta Sigma Modulators With A Plurality Of Switched Capacitor Return-to-zero Digital To Analog Converters

Continuous-time Delta Sigma Modulators With A Plurality Of Switched Capacitor Return-to-zero Digital To Analog Converters

Technology Category/Market

Technology: Continuous-time Delta Sigma Modulators With A Plurality Of Switched Capacitor Return-to-zero Digital To Analog Converters

Category: Electronics & Circuits

Industry: Electronic System & Design Manufacturing (ESDM),

Application: Analog-to-digital conversion (ADC).

Market: The Global Market Size of Delta-sigma Modulator was valued at USD 1.69 Billion in 2023 and is expected to reach USD 3.27 Billion by the end of 2030 with a CAGR of 7.7%

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Problem Statement

  • Delta-sigma data modulators are used in analog-to-digital conversion (ADC) applications due to their bandwidth and accuracy.
  • Continuous delta-sigma modulators (CTDSMs) are becoming attractive due to their power and area efficiency.
  • However, CTDSMs suffer from linearity and jitter performance due to full-scale steps in the feedback waveform.
  • Techniques like the switched-capacitor feedback DAC and the Return-to-Zero (SCRZ) DAC address this issue while achieving low jitter sensitivity.
  • These techniques provide poor alias rejection despite achieving low jitter sensitivity.

Technology

  • The present invention provides a continuous time delta-sigma modulator (CTDSM) with an input node for receiving input voltage, an integrator, a first sub-digital to analog converter (DAC), and a second sub-DAC.
  • The integrator includes an OTA and a feedback capacitor.
  • The first sub-DAC has a primary, secondary, tertiary, and quaternary auxiliary modules.
  • The second sub-DAC samples attenuated input voltage at a sampling rate with a delay
  • The method involves receiving an input voltage, sampling attenuated input voltage, and adjusting the sampling rate.
  • The invention is not limited to the described embodiments and can be modified without departing from the spirit.

CTDSM 200 Overview

  • Input node 202, integrator 204, feedback node 206, first sub-DAC 208a, second sub-DAC 208b.
  • Integrator 204 includes operational transconductance amplifier (OTA) 2041 and feedback capacitor 2042.
  • OTA 2041 has finite transconductance gm, feedback capacitor has capacitance ‘C’.
  • First sub-DAC 208a includes primary auxiliary and secondary modules.
  • Second sub-DAC 208a includes tertiary and quaternary modules

Key Features/Value Proposition

Current and Alis Rejection in Circuit

  • Current i1 and i2 are RZ pulses, half clock cycle wide.
  • Total current i1+i2 is a NRZ pulse.
  • Circuit 300 computes alias rejection at fs.
  • CTDSM 200 is excited with an input voltage.

Dual-SCRZ DAC for CTDSM

  • Proposed CTDSM with dual SCRZ DAC achieves infinite alias rejection, even with OTA having finite transconductance.
  • The dual SCRZ DAC samples the voltage of the virtual ground at two instances per cycle.
  • Combines low peak-to-average ratio of a non return-to-zero pulse with low jitter sensitivity of a switched capacitor feedback DAC.
  • Excellent alias rejection is obtained around fs, even with limited bandwidth of the OTA.
  • Measured results show improvements in linearity and alias rejection compared to a modulator using SCRZ DAC.
  • Dual SCRZ DAC is robust with respect to clock jitters.
  • Voltage of a virtual ground is sampled at two instances per cycle through the dual SCRZ DAC (208a, 208b) while consuming Lower power.
Questions about this Technology?

Contact for Licensing

Research Lab

Prof.  Shanthi Pavan

Department of Electrical Engineering.

Intellectual Property

  • IITM IDF Ref. – 1295

  • Patent No: IN – 482975

Technology Readiness Level

TRL-4

Experimentally validated in Lab

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IDF No 1553 Rotatable Heat Sink

Rotatable Heat Sink

Technology Category/Market

Category- Electronics & Circuits

Industry Classification:

NIC (2008)- 2610– Manufacture of electronic components

Applications:

Cooling of electronic devices such as mobile phones, reduction of temperature in avionics etc.

Market report:

The global market for heat sinks was estimated at USD 7.37 billion in 2023 and is projected to grow to USD 12.99 Billion by 2032 with a CAGR of 6.50%.

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Problem Statement

  • Heat sinks facilitate the heat generating elements on devices to dissipate heat by providing a larger heat transfer area.
  • However, these heat sinks were based on sensible heat causing the device temperatures to rise with time.
  • Phase Change Material (PCM) based heat sinks address the problem by absorbing latent heat. However, The major design goal in a PCM based heat sink would be to stretch the latent heat time during charging and to reduce the discharging cycle time.
  • A novel heat sink technology of air-based impeller type heat sinks have emerged. However, air and PCM based heat sinks have not been subject to rotation.
  • There is a need for a simple, effective and efficient heat sink with maximum operation time during heat cycle and minimum operation time during the cooling cycle.

Technology

  • The device comprises of heat sink capable of rotating and mounted on a motor, and a phase changing material stored within the heat sink. The sink is adapted to be in relative motion with respect to air to cool the component.
  • The sink preferably made of aluminum may be with or without an internal central stem and radial fins . The Phase Changing Material (PCM) is preferably n-eicosane which is filled in the cylinder at a number of ratios and may also be used at different orientations and rotational speeds.
  • Experimental investigations of the effect of fins, gravity, rotational convection and mass of the phase change material (PCM) on the thermal performance of a heat sink subjected to constant heat flux of 5 kW/m2 at the base were disclosed.
  • The heat sink was subject to four fill ratios (0, 0.33, 0.66,0.99) of PCM/air, nine orientations 25 (0,45,90,135,180,225,270, 315, 360), and three rotational speeds (0,60,120 RPM) simultaneously.
  • Regardless of the configuration, rotation has a positive effect of 25 % performance enhancement on melting, only at lower fill ratios. However, rotation was found to have a negligible effect at higher fill ratios.
  • A finned heat sink performs the best among the three chosen configurations with an enhancement ratio 10.25, while incurring highest cost.
  • There is always a conflict between the cost and the performance for all configurations. This can be resolved by the designer keeping in mind the application and the requirement.

Key Features/Value Proposition

  • The performance of PCM based heat sink is superior to air-based heat sink during the heating/melting cycle, and vice versa during the cooling/solidification cycle
  • The combined effects of latent and sensible heat is the best for a heat sink cylinder comprising both the PCM as well as fins as it makes use fins to spread the heat from the base uniformly in the PCM.
  • In real world applications the orientation of an un-finned heat sink containing a PCM can vary as per operating conditions. The enhancement ratio of the invented heat sink with 99% PCM fill is insensitive to orientation making it reliable from an engineering perspective.
  • The invented rotating heat sink addresses the problem of stagnant air near heat sink walls observed in conventional heat sinks.
  • The invention allows wide scope of customization based on various factors such as fill ratio, presence of fins and orientation for working out optimum performance and cost trade-offs.
Questions about this Technology?

Contact for Licensing

Research Lab

Prof. Chakravarthy Balaji

Department of Mechanical Engineering

Intellectual Property

  • IITM IDF Ref.1282
  • IN 352112 Patent Granted

Technology Readiness Level

TRL 3

Experimental Proof of concept

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IDF No 1091 A method of producing a linear current signal in a baseband Voltage – to-Current (V-I) converter

A method of producing a linear current signal in a baseband Voltage - to-Current (V-I) converter

Categories for this Invention

Technology: Voltage to current converter

Industry/Application: RF & Microwave systems, Communication Systems, Electric Vehicle, Medical Equipment, & etc.; 

Market: The global power converter market is projected to reach at a CAGR of 7.8% during the period (2024-32).

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Problem Statement

  • The problem statement discussed in the present invention is how to develop an up-conversion mixer with the improved linearity and power efficiency by employing a closed loop negative feedback control mechanism.
  • Hence, subject invention addresses the issue.

Technology

  • Present patent discussed a baseband Voltage-to-Current (V-I) converter.
  • Said V-I converter comprises a feedback converter configured to
  • receive at least one first current signal from at least one first power transistor in a first stage & at least one second current signal from at least one second power transistor in a second stage;
  • produce at least one feedback current signal in said first stage & said second stage by sensing said at least one first current signal from said at least one first power transistor in said first stage & said at least one second current signal from said at least one second power transistor in said second stage.
  • Said V-I converter comprises an operational amplifier configured to:
  • receive a plurality of said feedback current signals & at least one reference current signal obtained from at least one input voltage signal;
  • compare the reference current signal with received plurality of feedback current signals;
  • send an output voltage signal to the first power transistor in the first stage & the second power transistor in the second stage; and
  • produce a liner output current signal based on the output voltage signal.

Key Features / Value Proposition

  • Provides mechanism for an up-conversion mixer with the improved linearity and power efficiency by employing a closed loop negative feedback control mechanism.
  • Facilitates a baseband voltage–to–Current (V-I) converter operating in a class-AB mode.
  • Facilitates a single stage error amplifier to drive one or more power transistors to operate in negative feedback.
  • Said invention is invented a way to directly sense the current driven into the mixer switches (ip,bb and im,bb in FIG. 1)

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Nagendra Krishnapura

Department of Electrical  Engineering

Intellectual Property

  • IITM IDF Ref. 1091

  • IN Patent No. 481665 (Granted)

Technology Readiness Level

TRL-4

Technology validated in Lab

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IDF No 1339 Apparatus for varying resonant frequency in a multi-frequency radio frequency (RF) Micro-Electro-Mechanical System (MEMS) switch

Apparatus for varying resonant frequency in a multi-frequency radio frequency (RF) Micro-Electro-Mechanical System (MEMS) switch

Categories for this Invention

Technology:; Apparatus for varying resonant frequency in a multi-frequency RF Micro-Electro-Mechanical System (MEMS) switch

Industry/Application: RF MEMS Switch, ESDM;

Market: The global RF MEMS market is projected to reach at a CAGR of 13.08% during the period (2024-32).

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Problem Statement

  • The problem statement discussed in the present invention is how to vary resonant frequency in a radio frequency (RF) MEMS capacitive switch.
  • Hence, subject invention addresses the issue.

Technology

  • Present patent describes  an apparatus for varying resonant frequency in a multi-frequency radio frequency (RF) Micro-Electro-Mechanical System (MEMS) capacitive  switch. (Refer Fig.1 & Fig. 2)
  • The apparatus includes a multi-frequency RF MEMS capacitive switch, a plurality of floating metals spaced uniformly in the multi frequency RF MEMS capacitive switch, a lateral thermal actuator, a push-pull beam with a contact arm and a plane tip or a T-shaped tip and a buckling actuator.
  • The buckling actuator, the push-pull beam and the lateral thermal actuator are in the same horizontal plane in the initial state (ON –state of the switch).
  • Further, a first (1st) direct current (DC) voltage is applied to the lateral thermal actuator and a second (2nd) DC voltage is applied to the buckling actuator.
  • The buckling actuator buckles upward from a first (1st) position to a 2nd position when the second (2nd) DC voltage is applied to the buckling actuator.
  • The push-pull beam is pushed laterally by the lateral thermal actuator towards the plurality of floating metals when the 1st DC voltage is applied to the lateral thermal actuator.
  • The voltages can be applied to the buckling actuator and the lateral thermal actuator at the same time or at different times.
  • The former case, the distance of separation between the buckling actuator and the push-pull beam and the 1st  & 2nd  voltages to be applied on them are optimized so as to assure that the buckling actuator has moved upward displacing itself from the path of the push-pull beam.
  • The latter case, the distance of separation and the voltages are not time-dependent, unlike the former case.
  • Moreover, each of the floating metal is segmented.

Key Features / Value Proposition

  • The proposed method facilitates a plurality of floating metals spaced uniformly in the multi-frequency RF MEMS capacitive switch.
  • Provide the RF MEMS capacitive switch with a lateral thermal actuator, a push-pull beam with a contact arm and a buckling actuator to vary the resonant frequency of the RF MEMS capacitive switch.
  • Based on a position of the push-pull beam over the plurality of
  • floating metals, the resonant frequency of RF MEMS capacitive switch is varying,
  • Position of the push pull beam over the plurality of floating metals is varied by varying said first DC voltage applied to the lateral thermal actuator
  • Applocations : Stationary Dielectric on metal (DOM), ESDM,

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Amitava Das Gupta

Prof. Deleep R Nair

Department of Electrical Engineering

Intellectual Property

  • IITM IDF Ref. 1339

  • Patent No. 363823

Technology Readiness Level

TRL-4

Proof of Concept ready & validated

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IDF No 1866 A Dc-Dc Voltage Converting Apparatus & a Method of Operation Thereof

A Comprehensive Brain-inspired Computational Model for Spatial Navigation

Categories for this Invention

Category- Artificial Intelligence (AI) & Machine Learning / Automobile & Transportation

Industry Classification:

  • NIC (2008)- 26515- Manufacture of radar equipment, GPS devices, search, detection, navigation, aeronautical and nautical equipment; 6201 Computer programming activities
  • NAICS (2022)- 334511 Search, Detection, Navigation, Guidance, Aeronautical, and Nautical System and Instrument Manufacturing; 5415 Computer Systems Design and Related Services
  • Applications: Navigation module for planning and navigation in spatial navigation in autonomous applications including but not limited to, Cars, Drones, Underwater vehicles etc.
  • Market drivers:

    The global navigational systems market size is estimated at USD 44.38 billion in 2024, and is expected to reach USD 70.96 billion by 2029, growing at a CAGR of 9.84% during the period.

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Problem Statement

  • Brain Based Devices ( BBDs) incorporate a simulated brain or nervous system with detailed neuroanatomy and have a physical instantiation, called a morphology or phenotype, which allows active sensing and autonomous movement in the environment.
  • However, existing brain-inspired computational models are unable to provide an effective hierarchical reinforcement learning experience and are inefficient in handling complex real-time spatial navigation in wide range of autonomous applications.
  • There is a need for an improved computational model for spatial applications and an improved comprehensive brain-inspired computational model using hierarchical reinforcement learning for spatial navigation applications.

Technology

  • A Hierarchical Reinforcement Learning (HRL) framework is configured with a prefrontal cortex at a higher level and Basal Ganglia (BG) and Hippocampus (HC) at the lower level wherein the Hierarchical Reinforcement Learning (HRL) framework is implemented to understand the interaction between Basal Ganglia (BG), Cortical Network and the Hippocampus (HC) to provide real time and seamless spatial navigation in wide range of autonomous applications.
  • The Basal Ganglia (BG) operates on at least one sensory data including but not limited to visual and others sensory data to extract local spatial information and prescribe navigational actions towards an immediate goal. The state of the BG is a continuous variable, which represents the the position of the agent in the ambient space
  • The Hippocampus comprises a global spatial map “cognitive map” for planning navigation at a larger scale. The states of the Hippocampus correspond to the landmarks. The Basal Ganglia and Hippocampus (HC) forms a two-level hierarchical navigation module for planning and navigation in autonomous applications
  • The Basal Ganglia (BG) is thought to implement Reinforcement Learning which modulates the relation between stimulus and response using the reward feedback from the environment. The BG passes on the results of learning progressively to the cortex. In the early stages of learning, the BG influences the motor output predominantly, while in the later stages, the motor cortex dominates the output, with diminishing contribution from the BG
  • The Hippocampus (HC) receives inputs from the higher order or association areas of the parietal cortex and sends back projections to the same cortical areas. It also has bidirectional connections with the Prefrontal Cortex. Within the HC there are various hippocampus fields. It is proposed that the functional architecture of the HC is similar to BG

Key Features / Value Proposition

  • Brain-inspired computational model developed can effectively handle novel situations or process large data sets simultaneously. Whereas, logic-based machines face difficulties in programming for situations with broad parameters and changing contexts while algorithms have poor scaling properties and the time required to run them increases exponentially as the number of input variables grows.
  • The invented brain-inspired computational model developed using hierarchical reinforcement learning is capable of handling complex real-time spatial navigation for a wide range of applications. Whereas, conventional computational models are inefficient in handle complex real-time spatial navigation.

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Srinivasa Chakravarthy V

Department of Biotechnology

Intellectual Property

  • IITM IDF Ref.1854
  • IN 506437 Patent Granted

Technology Readiness Level

TRL 3

Experimental Proof of Concept

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IDF No 2529 A Signal Strength Indicator Circuit

A Signal Strength Indicator Circuit

Categories for this Invention

Technology: Signal Strength Indicator Circuit;

Industry/Application: Signal Strength detectors, signal-strength detector; CMOS inverter;

Market: The global market is projected to reach at a CAGR of 32.58% during the period (2024-32).

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Problem Statement

  • The problem statement discussed in the present invention is how to develop a topology where amplification and amplitude detection can be combined in a single block. .
  • Hence, subject invention addresses the issue efficiently.

Technology

  • Present patent discussed about a pseudo-differential amplifier chain.
  • Said pseudo-differential amplifier chain comprises a complementary metal oxide semiconductor (CMOS) inverter pair as amplifier, configured to receive a differential signal.
  • Further, it includes a voltage regulator unit connected to the pseudo-differential amplifier chain to provide a supply voltage Vs for biasing the pseudo-differential amplifier at a reference Direct current (DC) operating point.
  • Moreover, the pseudo-differential amplifier chain includes a current mirror circuit connected with the pseudo-differential amplifier chain to receive a supply current from the pseudo-differential amplifier chain & generate a mirrored output current.
  • The mirrored output current is used to determine strength of the differential signal.

Key Features / Value Proposition

  • Integrates amplification & amplitude detection in a single unit. CMOS inverters can be more easily designed at low supply voltages than other types of amplifiers.
  • Develops a signal-strength detector utilising low power.
  • The signal-strength detector circuit occupies 0.08 mm2, consumes 1.2 mW from 1.5V and
  • the noise floor is 0.2mV rms. (Refer Table1)
  • Facilitates a compact signal-strength detector.
  • More amenable to low supply voltage operation.
  • A 65nm prototype of the
  • signal-strength detector circuit has a 70.9dB dynamic range with ±1dB error.

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Nagendra Krishnapura

Department of Electrical Engineering

Intellectual Property

  • IITM IDF Ref. 2529

  • Patent No. 545473  

Technology Readiness Level

TRL – 4

Technology validated in lab scale.

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IDF No 2301 System and Method for Continuous-time Pipeline ADC With Reduced In-Band Transfer-function Droop

System and Method for Continuous-time Pipeline ADC With Reduced In-Band Transfer-function Droop

Categories for this Invention

Category- Analog-to-Digital Conversion (ADC) Systems

Applications – Communications, Industrial Automation

Industry – Telecommunications, Healthcare, Automotive Electronics

Market – The analog to digital converter market is anticipated to flourish at an average CAGR of 5.7% between 2023 and 2033 and is likely to reach a value of US$ 3.51 billion in 2023.

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Problem Statement

  • The use of identical stages in a multi-stage Continuous-Time Pipelined (CTP) Analog-to-Digital Converter (ADC) leads to a notable in-band droop, causing a detrimental impact on both the Signal-to-Quantization Noise Ratio (SQNR) and overall conversion performance.
  • While some existing multi-stage CTP ADCs utilize impedance scaling and second-order Butterworth stages to alleviate droop, they are limited in fully addressing the cumulative droop throughout the entire pipeline, especially when multiple stages are cascaded together.
  • Moreover, the droop present in the filter transfer function within the signal band can result in a decrease in SQNR, especially affecting input frequency components near the band-edge frequency. This can greatly impede the converter’s reliability when it comes to various input variations.

Technology

  • The present invention discloses a system and method for a continuous-time pipeline (CTP) analog-to-digital converter (ADC) which comprises the benefits of pipelining with continuous-time operation.
  • The system incorporates at least one pipeline stage configured with non-identical amplifier filters, achieving a unique transfer function for each stage to reduce in-band transfer function droop.
  • By utilizing non-identical residue amplifying filters in each pipeline stage, the system effectively reduces droop in the signal band, enhancing overall performance.
  • The system features a computing application capable of determining the number of stages and filters, analyzing the non-identical transfer function, and determining transfer functions for non-identical pipeline stages.
  • Unlike conventional approaches, the system is designed to realize an overall transfer function rather than selecting transfer functions for individual pipeline stages.
  • The method provides flexibility by allowing the use of non-identical residue-amplifying filters such as Butterworth and Chebyshev filters, catering to user or application-specific requirements. The overall Butterworth design achieves higher Signal to Quantization Noise Ratio with lower droop at the band edge.

Key Features / Value Proposition

Market Advantage:

  • Enhanced Performance: Non-identical transfer functions in each stage reduce in-band droop, improving Signal-to-Quantization Noise Ratio (SQNR) and overall ADC performance.

Key Features:

  • Continuous-Time Operation: Leverages the benefits of continuous-time operation in a pipeline ADC, combining efficiency with high-speed conversion.
  • Tailored Transfer Functions: Appropriate design of non-identical transfer functions per stage optimizes the equivalent anti-alias filter, maintaining high-frequency attenuation while minimizing in-band droop.

Competitive Edge:

  • Adaptive Butterworth Function: Realizes an overall Butterworth transfer function, offering a competitive advantage over systems with individually chosen Butterworth transfer functions for each stage.

Industry Innovation:

  • Integrated System Design: The CTP ADC system integrates non-identical filters and backend ADC seamlessly, presenting an innovative solution for improved performance without sacrificing design simplicity.

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Shanthi Pavan

Department of Electrical Engineering

Intellectual Property

  • IITM IDF Ref. 2301
  • IN 441016 – Patent Granted

Technology Readiness Level

TRL – 4

Technology validated in lab scale.

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IDF No 1922 Varying Carrier based Pulse Width Modulation Technique for Multisource Inverter System

Varying Carrier based Pulse Width Modulation Technique for Multisource Inverter System

Categories for this Invention

Category – Photovoltaic Systems and Power Electronics, Electronics & Circuits

Applications – Solar Power Systems, Microgrids, Electric Vehicle Charging Stations

Industry – Renewable Energy, Automotive and Transportation

Market- The Maximum Power Point Tracking Charge Controllers Market is expected to grow at a CAGR of 10% from 2024 to 2031.

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Problem Statement

  • Two-stage power converter systems, involving both DC-DC converters and inverters, are complex and expensive compared to simpler single-stage systems.
  • Existing maximum power point tracking (MPPT) techniques, like perturb and observe (P&O), suffer from inefficiencies due to oscillations around the maximum power point (MPP).
  • Parallel connections of photovoltaic panels increase conduction losses and are restricted by differing voltage ratings, while series connections necessitate multiple converters, raising component count and cost.

Technology

  • The invention provides a method for maximum power point tracking (MPPT) in photovoltaic-fed single-stage multisource inverters by determining and comparing reference voltages for multiple photovoltaic panels to optimize power extraction and efficiency.
  • It introduces control parameters (first and second) that measure differences between actual and reference voltages, using these to generate pulse width modulated gate signals for semiconductor switches, thereby optimizing power delivery to the load or grid.
  • The system employs a varying carrier-based pulse width modulation (PWM) technique to manage the connection and current supply duration of each photovoltaic panel, enhancing the inverter’s overall performance and power extraction capabilities.

Key Features / Value Proposition

1. Enhanced Power Efficiency:

  • Maximizes power extraction from photovoltaic panels using advanced MPPT techniques, ensuring optimal energy conversion.

2. Cost Reduction:

  • Simplifies system architecture with single-stage multisource inverters, reducing component count and overall system costs.

3. Innovative Control Parameters:

  • Utilizes first and second control parameters to precisely regulate voltage levels and optimize power delivery.

4. Dynamic PWM Modulation:

  • Employs varying carrier-based pulse width modulation (PWM) to efficiently manage current supply duration for each panel.

5. Improved Performance Stability:

  • Minimizes oscillations around the maximum power point (MPP) with sophisticated voltage comparison methods.

6. Scalability and Flexibility:

  • Supports multiple photovoltaic panels with series connections, offering scalable and flexible solutions for high-power applications.

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Lakshminarasamma

Prof. Mahesh Kumar

Department of Electrical Engineering

Intellectual Property

  • IITM IDF Ref. 1922
  • IN 466107 – Patent Granted

Technology Readiness Level

TRL – 4

Technology validated in lab scale.

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IDF No 1780 A System and Method for Obtaining Bipolar Voltage Output

A System and Method for Obtaining Bipolar Voltage Output

Categories for this Invention

Category – Power Electronics, Electronics & Circuits

Applications– Ion Analyzers and Spectrometers,

Smart Material Actuators, Pulsed Electric Field (PEF) Applications

Industry- Renewable Energy and Smart Grids

Market – Power Electronics Market Size is projected to grow from USD 46.2 Billion in 2023 to USD 61.0 Billion by 2028;, at a CAGR of 5.7%.

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Problem Statement

  • Conventional power supplies and methods for achieving bipolar high voltage output are inadequate for applications requiring controlled, continuous bipolar voltage with lower dv/dt rates and reduced peak power.
  • Complexity and Inefficiency: Existing solutions, involving series configurations of boost stages and output stages, are complex, inefficient, and primarily designed for pulsed load applications, making them unsuitable for steady-state bipolar HV requirements.

Technology

  • The present invention relates to a system and a method for obtaining bipolar voltage output.
  • The system uses first and second bidirectional converter modules, each featuring a bidirectional flyback converter and comparators, to achieve precise control of bipolar voltage output.
  • A controller, executing instructions from memory, assigns positive and negative values to the respective converter modules based on a predefined reference voltage, ensuring accurate voltage output by operating in charge, refresh, or discharge modes.
  • The method involves selecting and comparing present output voltage against the reference voltage for each converter module, dynamically adjusting operation modes to maintain desired bipolar voltage profiles.

Key Features / Value Proposition

1. Precise Voltage Control:

  • Provides accurate bipolar voltage output through dynamic management of bidirectional converter modules, ensuring reliable performance for advanced applications.

2. Enhanced Efficiency:

  • Reduces energy losses by dynamically adjusting the operation modes (charge, refresh, discharge) based on real-time voltage comparisons, optimizing power usage.

3. Versatile Application Compatibility

  • Supports diverse high voltage applications like ion analyzers, smart material actuators, and pulsed electric field processes, enhancing its market appeal.

4. Simplified System Architecture:

  • Integrates bidirectional flyback converters and comparators within each module, streamlining the system design and reducing complexity.

5. Improved Operational Flexibility:

  • Assigns and manages positive and negative voltage profiles independently, offering greater flexibility in meeting specific operational requirements.

6. Autonomous Operation Capability:

  • Incorporates smart control circuitry for autonomous voltage regulation, minimizing the need for external intervention and maintenance.

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Lakshminarasamma

Department of Electrical Engineering

Intellectual Property

  • IITM IDF Ref. 1780
  • IN 479043 – Patent Granted

Technology Readiness Level

TRL – 4

Technology validated in lab scale.

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IDF No 2682 Repetition rate Independent Stabilization of Active Harmonic mode-Locked Fiber Laser

Repetition rate Independent Stabilization of Active Harmonic mode-Locked Fiber Laser

Categories for this Invention

Technology: Stabilization of Active Harmonic mode-Locked Fiber Laser

Category: Electronics & Circuits /Photonics

Industry: Electronic System & Design Manufacturing (ESDM)

Application: Mode-locked lasers, Photonic analog to digital converter, optical communications

Market: The global market size valued at USD 3.86 Billion in 2022 and is poised to grow from USD 4.31 Billion in 2023 to USD 10.36 Billion by 2031, at a CAGR of 11.6% during the forecast period (2024-2031).

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Problem Statement

  • Mode locked lasers have revolutionized various technologies, producing ultrashort optical pulses with pulse repetition rates between 50 MHz and a few gigahertz (GHz).
  • Active mode locking techniques can generate GHz repetition rates without shortening the optical cavity length, while harmonic mode locking aims for higher pulse repetition rates using an RF source.
  • However, these lasers can be unstable in the long term due to continuous fluctuations in the cavity’s FSR due to environmental disturbances, temperature fluctuations, and vibrations.
  • A control system is needed to stabilize active harmonic mode-locked lasers, maintain long-term operation, and enhance performance reliability, particularly for applications like photonic analog-digital converters, optical clock distribution, and microwave signal generation.

Technology

Process flow for stabilization of the AHML:

  • Monitoring an integrated optical power in the lower-order longitudinal cavity modes
  • Determining a threshold integrated power of the lower-order longitudinal cavity modes as an indicator of pulse stability
  • Converting the integrated optical power of the lower-order longitudinal cavity modes into an electrical signal
  • Receiving the converted electrical signal and determining an instantaneous RF power level at the RF power meter
  • Digitizing the instantaneous RF power level output of the RF power meter by the ADC
  • Generating a DAC correction voltage based on the instantaneous RF power level and a control logic
  • Generating a DAC output voltage as a feedback correction signal based on the control logic
  • Sending the DAC output voltage to a piezo electric transducer (PZT) fiber stretcher of the AHML
  • Controlling a cavity length of the PZT based fiber stretcher to achieve a longitudinal mode spacing as an integral multiple of a desired pulse repetition rate
  • Minimizing the integrated optical power of lower-order longitudinal cavity modes of the AHML.

Key Features / Value Proposition

Active Harmonic Mode-Lock Laser Operation

  • Minimize integrated optical power of lower-order longitudinal cavity modes.
  • Ensure reliable, stable operation for longer, uninterrupted duration.
  • Maintain stability without performance impact from environmental disturbances.

Stabilizing Active Harmonic Mode-Locked Fiber Laser

  • Functions regardless of repetition rates.
  • Eliminates need for reconfiguration.
  • Avoids cavity length and FSR variations.

Configuring ADC for RF Power Levels

  • Receives instantaneous RF power levels.
  • Determines desired RF power level.

Maintaining RF Power Level Threshold at ADC

  • Maintains desired threshold for 1800s.

RF Power Level Measurement

  • Measures difference between instantaneous and desired levels.
  • Determines desired RF power level threshold.
  • Maintains instantaneous RF power level at determined threshold.

RF Power Level Monitoring

  • Controls DAC output voltage and integrated optical power.

Terminates DAC correction voltage generation

  • if ADC voltage reaches PZT limit.

Photodetector operates at

  • bandwidth of less than 400MHz.

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Deepa Venkitesh

Prof. Balaji Srinivasan

Department of Electrical Engineering

Intellectual Property

  • IITM IDF Ref. 2862

  • Patent No: IN 545507

Technology Readiness Level

TRL- 3

Experimental Proof of concept

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IDF No 2111 White Light Emission From Single Semiconductor Material Based On Trivalent Mixed Halide Double Perovskites

White Light Emission From Single Semiconductor Material Based On Trivalent Mixed Halide Double Perovskites

Categories for this Invention

Categories: Electronics & Circuits | Photonics

Industry: Semiconductor Materials, Solid-State Lighting (SSL) Technology

Application: White Light Emitting Devices

Market:  The global Energy Efficient Lighting market size was valued at $53.98 B in 2023 and is expected to touch $93.12 B by 2030 growing at 8.1% CAGR in the forecasted period.

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Problem Statement

  • Current methods for making white light devices involve complicate manufacturing process using multiple materials.
  • Existing materials have problems like instability and inconsistency, making it hard to create reliable white light devices.
  • Many potential materials cannot be made in large amount, limiting mass production use.
  • Traditional white light production techniques are not energy-efficient.
  • Current lighting methods contribute to pollution without any optimal result production.
  • Thus, Developing better white light devices is important for sustainability.
  • Hence, the present patent disclosure is needed to improve energy efficiency and enhance reliability of white light emitting devices by providing single semiconductor material capable streamline manufacturing of emitting white light.

Technology

The instant technology disclosure encompasses a semiconductor material based on trivalent mixed halide double perovskites for white light emission & methods for thin film deposition and device fabrication.

  • The technology involves a semiconductor compound based on trivalent mixed halide double perovskites, with a specific formula (Cs2AgM11-xM2xCl6).
  • This compound emits white light efficiently, making it suitable for lighting applications.
  • The compound can be synthesized using a hydrothermal method, producing powder, single crystal, or thin film forms.
  • Thin films of the compound can be deposited on conducting or semiconducting substrates using electrophoretic deposition or dip coating methods.
  • The compound, when combined with transparent polymers, can be used to fabricate white light-emitting devices, like LEDs, through dip coating processes.

Key Features / Value Proposition

  • Efficiency: Provides a single semiconductor material for white light emission in simple processes.
  • Energy Savings: Enhances energy efficiency in lighting applications, reducing electricity consumption.
  • Reliability: Offers stable and reproducible performance, improving the longevity of lighting devices.
  • Environmental Impact: Reduces environmental footprint through lower energy consumption.
  • Cost-efficiency: Reduces manufacturing costs by streamlining processes and utilizing fewer materials, resulting in more affordable white light emitting devices.
  • Versatility: Applicable in residential, commercial, industrial, automotive, healthcare, displays, etc.

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Aravind Kumar Chandiran

Department of Chemical Engineering.

Intellectual Property

  • IITM IDF No.: 1906 | IP No.: 493546 (Granted)
  • PCT: PCT/IN2020/050951

Technology Readiness Level

TRL – 4

Experimentally validated in lab.

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IDF No 2058 Method and Hybrid Beam Combining System to Obtain High Power Laser Beam

Method and Hybrid Beam Combining System to Obtain High Power Laser Beam

Categories for this Invention

Category – High-Power Laser Systems

Applications –  Industrial Manufacturing, Laser Surgery and Treatments, Non-Invasive Diagnostics

Industry- Precision Cutting and Welding, Advanced Photonic Components

Market – Global High Power Laser Systems Market is expected to register a CAGR of 7.1% during the forecast period (2022-2027).

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Problem Statement

  • Individual laser emitters and single-mode fiber lasers face power limitations due to thermal and nonlinear effects, restricting their effectiveness for Directed Energy (DE) applications.
  • Coherent beam combining (CBC) of multiple laser modules is needed to achieve high power levels, but it faces issues like stringent requirements on laser parameters, nonlinear optical effects, and practical difficulties in phase noise compensation and beam quality.
  • Phase synchronization time and the number of iterations required increase with more elements, complicating the system’s scalability and affecting the overall beam quality and efficiency.

Technology

  • The system utilizes multiple master oscillators to split each laser beam into two beams, amplifying them separately and coherently combining them through multiple stages to achieve high-power output.
  • It employs feedback controllers and beam quality monitors for phase synchronization and quality maintenance, utilizing machine learning techniques like Recurrent Neural Networks (RNNs) to optimize performance.
  • The system can produce a high power composite laser beam, ranging from 10 Watts to several MegaWatts, by polarization multiplexing and spectrally combining the coherently combined beams from each laser.

Key Features / Value Proposition

1. Enhanced Power Output:

  • Achieves high-power laser beams suitable for demanding applications, ranging from 10 Watts to several MegaWatts.

2. Superior Beam Quality:

  • Utilizes advanced phase synchronization and feedback control systems to maintain optimal beam quality and minimize power losses.

3. Scalability and Flexibility:

  • Scalable architecture allows for easy integration and adaptation to various industrial, defense, and research applications.

4. Advanced Control with AI:

  • Incorporates machine learning techniques, such as Recurrent Neural Networks (RNNs), for improved phase synchronization and system optimization.

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Balaji Srinivasan

Department of Electrical Engineering

Intellectual Property

  • IITM IDF Ref. 2058
  • IN 507846 – Patent Granted

Technology Readiness Level

TRL – 5

Technology validated in relevant environment.

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IDF No 1804 Hybrid Power Filtering Unit Incorporating Low Power, Fast Switching Converter in Conjunction with High Power, Slow Switching Converter

Hybrid Power Filtering Unit Incorporating Low Power, Fast Switching Converter in Conjunction with High Power, Slow Switching Converter

Categories for this Invention

Category – Power Electronics, Electronics & Circuits

Applications – Industrial Power Systems, Renewable Energy Systems, Electric Vehicle Charging Stations, HVAC Systems

Industry – Energy & Utilities

Market – HVAC market size was worth over USD 294 billion in 2023 and is estimated to expand at 5.6% CAGR from 2024 to 2032

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Problem Statement

  • Converters and inverters cause harmonic distortion in AC power supplies, leading to equipment overheating and power failures.
  • Si IGBT-based converters are limited by their switching frequency, making them inefficient for higher-order harmonic mitigation.
  • There is a need for a hybrid power filtering unit that combines low-power, fast-switching SiC MOSFET converters with high-power, slow-switching Si IGBT converters to improve harmonic rejection and compactness.

Technology

Hybrid Filter Design:

  • Combines a high-capacity Si IGBT converter for lower-order harmonics (5th and 7th) with a smaller, fast-switching SiC MOSFET converter for higher-order harmonics (11th, 13th).

Efficiency and Loss Management:

  • The Si IGBT converter operates at a low switching frequency, reducing switching losses, while the SiC MOSFET converter operates at a high frequency for efficient higher-order harmonic elimination.

Parallel Configuration:

  • The SiC MOSFET converter is retrofitted in parallel with the Si IGBT converter, optimizing harmonic filtering across different frequency ranges.

Key Features / Value Proposition

1.Comprehensive Harmonic Mitigation:

  • Effectively eliminates both lower-order (5th, 7th) and higher-order (11th, 13th) harmonics through a dual-converter approach.

2. Optimized Efficiency:

  • Utilizes a high-capacity Si IGBT converter for lower-order harmonics to minimize switching losses while achieving high efficiency.

3. Advanced High-Frequency Filtering:

  • Incorporates a small, fast-switching SiC MOSFET converter to handle high-frequency harmonic components, enhancing overall performance.

4. Cost-Effective Solution:

  • Balances the use of cost-effective Si IGBT technology with the advanced capabilities of SiC MOSFETs, offering a high-performance yet economical solution.

5. Parallel Configuration Benefits:

  • The parallel setup of converters maximizes harmonic rejection across various frequency ranges, ensuring a cleaner power supply.

6. Scalable and Retro-Fittable:

  • Designed to be easily retrofitted into existing systems, allowing for seamless integration and scalability based on power requirements.

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Kamalesh Hatua

Department of Electrical Engineering

Intellectual Property

  • IITM IDF Ref. 1804
  • IN 504454 – Patent Granted

Technology Readiness Level

TRL – 5

Technology validated in relevant environment.

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IDF No 1545 Accurate Determination of Brillouin Frequency in Brillouin Distributed Fiber Sensors using Cross Recurrence Plot Analysis

Accurate Determination of Brillouin Frequency in Brillouin Distributed Fiber Sensors using Cross Recurrence Plot Analysis

Categories for this Invention

Category – Fiber Optic Sensing

Applications – Structural Health Monitoring,

Power Grid & Geotechnical Monitoring

Industry- Telecommunications, Energy and Utilities, structural monitoring

Market Global Fiber Optic Sensors Market to Reach $605.4 Million by 2032 with a CAGR of 6.2%

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Problem Statement

  • Conventional distributed Brillouin sensors face accuracy limitations due to very low signal-to-noise ratios (SNR), especially at the farther end of the sensing fiber.
  • Standard methods like quadratic fitting are error-prone with low SNR signals, leading to inaccuracies in Brillouin frequency shift (BFS) estimation.
  • Existing techniques need enhancement to accurately measure BFS over long distances with low SNR, with cross-correlation methods showing promise for improving measurement accuracy.

Technology

  • Brillouin Scattering and Frequency Shift Measurement: The process involves initiating Brillouin scattering in an optical fiber by propagating an intense optical signal, generating backscattered light with a frequency shift indicative of local acoustic velocity.
  • Cross Recurrence Plot Analysis (CRPA): The method uses CRPA to compute the Brillouin frequency at various locations along the sensing fiber by comparing a reference spectrum (Lorentzian, Gaussian, or Voigt lineshape) with the measured spectrum. This technique enhances the accuracy of frequency measurement even with low signal-to-noise ratios (SNR <10 dB).
  • Enhanced Measurement Accuracy: The process is designed to work effectively with distorted Brillouin gain spectra and uses frequency steps greater than 1 MHz.

Key Features / Value Proposition

Enhanced Accuracy:

  • Utilizes Cross Recurrence Plot Analysis (CRPA) to accurately measure Brillouin frequency shifts, improving precision even in low signal-to-noise ratio conditions.

High Sensitivity:

  • Capable of detecting small changes in temperature and strain with high sensitivity by analyzing the Brillouin gain spectrum.

Robust Performance:

  • Effective in environments with distorted Brillouin gain spectra, maintaining reliable measurements under challenging conditions.

Flexible Spectrum Analysis:

  • Supports various reference spectrum types (Lorentzian, Gaussian, Voigt), providing versatility in different sensing applications.

Large-Scale Monitoring:

  • Suitable for distributed sensing along extensive optical fiber lengths, enabling comprehensive monitoring of large infrastructures.

Advanced Data Processing:

  • Employs advanced signal processing techniques to handle low SNR measurements, enhancing the overall performance and accuracy of Brillouin distributed sensors.

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Balaji Srinivasan

Department of Electrical Engineering

Intellectual Property

  • IITM IDF Ref. 1545
  • IN 379844 – Patent Granted

Technology Readiness Level

TRL – 5

Technology validated in relevant environment.

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IDF No 1327 Floating Wiper Inductive Voltage Divider Type Displacement Transducer

Floating Wiper Inductive Voltage Divider Type Displacement Transducer

Categories for this Invention

Technology: Floating Wiper Inductive Voltage Divider Type Displacement sensor;

Industry/Application: Automotive Industry, Aerospace, Defense, Medical & Industrial-Oil & Gas;

Market: The global displacement sensor market is projected to reach at a CAGR of 8.9% during the forecast period (2024-30).

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Problem Statement

  • The problem statement discussed in the present invention is how to configure inductive voltage divider type sensor configured for detecting displacement in the jet engines in effective manner. 
  • Hence, claimed invention addresses the issue.

Technology

Present patent describes a discloses an inductive voltage divider type sensor configured for detecting displacement.

The sensor circuit comprises:

  • The disclosed inductive voltage divider type sensor has capability for sensing either unipolar or bipolar displacement. (Refer Fig.1, and Fig.3)
  • Further subject invention relates to a displacement sensor that has an inductive voltage divider type sensing unit and a signal conditioning circuit.
  • The inductive voltage divider type sensing unit includes an inductive element that has a single wound coil having an axis that terminate at a first end & a second end.
  • A contactless wiper is placed at a fixed distance from the axis of the coil and is configured to be displaced laterally in a plane parallel to the axis of the coil. (Refer Fig.2)

Key Features / Value Proposition

  • Increased operational life. And Provides better accuracy;
  • Consumes less power, and Suitable for precision instrumentation;
  • Reduced weight & compact size.
  • Applicable in precision measurements in industrial, automotive, medical, utility, scientific, oil and gas sectors in particular Aerospace, Defense, Medical & Industrial.

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Jagadeesh Kumar V

Prof. Boby George

Department of Electrical Engineering.

Intellectual Property

  • IITM IDF Ref. 1327

  • IN Patent No. 490651

Technology Readiness Level

TRL-4

Technology validated in Laboratory

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IDF No 2789 Pseudo-interdigitated-corbino Thin Film Transistor with Multi-finger Source and Drain Electrical Contacts

Pseudo-interdigitated-corbino Thin Film Transistor with Multi-finger Source and Drain Electrical Contacts

Categories for this Invention

Category- Electronics & Circuits

Industry Classification:

  • NIC (2008)-2610- Manufacture of electronic components
  • NAICS (2022)- 334413- Semiconductor and Related Device Manufacturing; 333242- Semiconductor Machinery Manufacturing

Applications: Manufacture of Semiconductors, Thin Film Transistors (TFTs), micro-fluidic devices, electrodes, LED displays, RF-ID tags, flexible electronics and communication devices such as antennas, frequency selective surfaces etc.

Market drivers:

Global Thin Film Transistor market was valued at USD 180.9 Million in 2023 and is expected to grow to USD 821.5 Million by the end of 2030 with a CAGR of 24.2%

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Problem Statement

  • Thin film transistors (TFTs) are being widely used for various electronic applications. Achieving the three desirable properties of- high transconductance, infinite output resistance, and reduced parasitic leakage in a limited layout space helps in adapting TFTs for logic-TFT or driver-TFT applications.
  • TFTs with interdigitated electrodes and Corbino geometry may enable increase in transconductance and reduction in parasitic leakage current with infinite output resistance respectively.
  • However, conventional technologies despite using low-cost polymeric semiconductors and Corbino geometry are able to achieve only infinite output resistance while not addressing the desired properties of high transconductance and reduction in parasitic leakage.
  • There is a need for a simple fabrication approach to simultaneously achieve excellent electrical isolation, increased transconductance and infinite output resistance while accommodating a large channel width.

Technology

  • The novel Psuedo-interdigitated-corbino TFT architecture comprises an arrangement of the source and drain electrodes to accommodate the large channel width (W) of the TFT in an enclosed interdigitated pattern. It is achieved by realizing an equivalent pseudo-corbino structure design as a combination of half-corbino structure and overlapping linear channels.
  • TFT using the novel Pseudo-interdigitated-corbino architecture results in infinite output resistance, providing constant drain output current in the saturation region independent of drain bias
  • The width of the overlapping linear channel region, denoted as WOV should be equal to or greater than two times the WS For a pseudo-interdigitated-corbino architecture with “n” number of interdigitated overlapping linear channels, the total channel width Wt is given by {n.WOV + (n−2).WS}, where “n” is the number of interdigitated overlapping linear channels.
  • The average width of half of the corbino disk (WS) is calculated using the middle circumference approximation {π(R1+R2)/2} as a function of geometrical parameters R1 and R2 i.e., the inner and the outer radius of half of the corbino disk with average channel width WS
  • The semiconductor layer is formed over or below the said source and drain electrodes in the top-gate top-contact, top-gate bottom-contact, bottom-gate bottom-contact, or bottom-gatetop-contact configuration.

Key Features / Value Proposition

  • The architecture comprises a more readily manufacturable TFT architecture that offers infinite output resistance to provide constant drain current in the saturation region.
  • The device showed excellent performance in terms of the device parameters. Whereas, none of the conventional methods overcome the limitations of multi-finger and Corbino TFT architectures in attaining excellent electrical isolation, increased transconductance and infinite output resistance, simultaneously, while accommodating high W/L ratio
  • The novel Pseudo-interdigitated-corbino architecture results in an easily manufacturable TFT architecture with reduced fabrication process steps compared to conventional Corbino TFT architecture.

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Soumya Dutta

Department of Electrical Engineering

Intellectual Property

  • IITM IDF Ref.2789
  • Patent Application No: IN 202441025688

Technology Readiness Level

TRL- 4

Experimentally validated in Lab

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IDF No 2268 Method for Mask-less Laser-assisted Hybrid Etching for Interdigitated Electrodes in Semiconductor Devices and Device thereof

Method for Mask-less Laser-assisted Hybrid Etching for Interdigitated Electrodes in Semiconductor Devices and Device thereof

Categories for this Invention

Category- Electronics and Circuits

Industry Classification:

  • NIC (2008)- 26101- Manufacture of electronic capacitors, resistors, chokes, coils, transformers (electronic) and similar components
  • NAICS (2022)- 333242- Thin layer deposition equipment, semiconductor, manufacturing
  • Applications: Manufacture of semiconductors-organic field-effect transistors (OFETs), interdigitated back contact (IBC) solar cells and communication devices such as antennas, frequency selective surfaces etc
  • Market drivers:

    The Semiconductor Etch Equipment Market size is estimated at USD 23.80 billion in 2024, and is expected to reach USD 34.32 billion by 2029, growing at a CAGR of 7.60%

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Problem Statement

  • Various approaches, such as subtractive processes and additive processes, are used for the fabrication of micro-channels or micro scribing on copper films.
  • However subtractive techniques such EDM and ECM have limitations in terms of minimum achievable feature size and micro-tool fabrication respectively.
  • Additive techniques such as laser additive manufacturing and vapor deposition techniques require masks and are prone to chamber contamination.
  • Photolithography and chemical etching techniques have limited scope due to use of masks and toxic nature of etchants respectively.
  • there is need for a system and method for mask-less etching which is reliable and does not suffer from the problems discussed above.

Technology

  • Submerging a metal film to be etched in a neutral salt solution.
  • Applying a voltage to an electrode unit, below a threshold voltage.
  • Focusing a laser beam through the electrode unit onto the metal film.
  • Irradiating the laser beam onto the metal film to increase the temperature around the ablation zone, along with laser ablation of the metal film
  • Triggering mobility of metal ions in the neutral salt solution for achieving selective chemical etching
  • Achieving hybrid mask-less removal of material from the metal film through laser ablation and laser-activated selective chemical etching

Key Features / Value Proposition

  • The developed hybrid micro-scribing technique is helpful in micro-scribing Cu film on a dielectric insulator without thermal damage to the dielectric substrate.
  • The developed method is mask-less and uses non-toxic reagents. Whereas, conventional methods require micro-tool fabrication or mask-based methods with toxic chemicals.
  • Overall, the device demonstrated a decent transistor characteristic with acceptable leakage current levels. The field-effect saturation mobility was estimated to be around 10-6 cm2/V s.
  • The proposed laser-assisted hybrid scribing is a promising technique for fabricating electrodes for semiconductors. The method is flexible, cost effective and environmental friendly.

Questions about this Technology?

Contact For Licensing

sm-marketing@imail.iitm.ac.in
ipoffice2@iitm.ac.in

Research Lab

Prof. Nilesh Jayantilal Vasa

Department of Engineering Design

Prof. Soumya Dutta

Department of Electrical Engineering

Intellectual Property

  • IITM IDF Ref.2268
  • IN 499893Patent Granted

Technology Readiness Level

TRL 4

Technology Validated in Lab

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